The Collier Report of U.S. Government Contracting

Sampling of Federal Government Funding Actions/Set Asides

In order by amount of set aside monies.

• $50,000 - Wednesday the 8th of October 2014
  National Aeronautics And Space Administration
  NASA SHARED SERVICES CENTER
  WE WILL IMPLEMENT AN ENVIRONMENT FOR DESIGN, FORMAL VERIFICATION, COMPILATION OF CODE, AND PERFORMANCE AND POWER EVALUATION OF SYSTEMS ON A CHIP (SOCS) CONSISTING OF HETEROGENEOUS PROCESSOR CORES THAT CAN BE SINGLE-ISSUE PIPELINED, SUPERSCALAR, OR VLIW, AND ARE BINARY-CODE COMPATIBLE WITH ANY EXISTING INSTRUCTION SET ARCHITECTURE (ISA). PARTICULARLY, WE WILL ENSURE BINARY-CODE COMPATIBILITY WITH THE POWERPC 750 ISA, WHICH IS USED IN THE RADIATION-HARDENED RAD750 FLIGHT-CONTROL COMPUTER THAT IS UTILIZED IN MANY NASA SPACE MISSIONS, INCLUDING DEEP IMPACT, THE MARS RECONNAISSANCE ORBITER, THE MARS ROVERS, AND IS PLANNED TO BE USED IN THE CREW EXPLORATION VEHICLE (CEV). THE PROCESSOR CORES WILL HAVE RECONFIGURABLE FUNCTIONAL UNITS AND CORRESPONDING SPECIALIZED INSTRUCTIONS THAT CAN BE OPTIMIZED TO ACCELERATE ANY APPLICATION. OUR FOCUS IN THIS PHASE 2 PROJECT WILL BE ON SOFTWARE DEFINED RADIO (SDR) APPLICATIONS. THE RADIATION-HARDENING WILL BE DONE AT THE MICROARCHITECTURAL LEVEL WITH A MECHANISM THAT WILL ALLOW THE DETECTION AND CORRECTION OF ALL TIMING ERRORS---CAUSED NOT ONLY BY RADIATION, BUT ALSO BY VARIATIONS IN THE VOLTAGE, FREQUENCY, MANUFACTURING PROCESS, AND AGING OF THE CHIP. THE BINARY-CODE COMPATIBILITY OF THE PROCESSOR CORES WITH THE POWERPC 750 ISA WILL ALLOW THEM TO SEAMLESSLY EXECUTE LEGACY BINARY CODE FROM PREVIOUS SPACE MISSIONS. WE HAVE MADE CRITICAL CONTRIBUTIONS TO THE FIELDS OF FORMAL VERIFICATION OF COMPLEX PIPELINED MICROPROCESSORS, AND BOOLEAN SATISFIABILITY (SAT), AND HAVE DEVELOPED HIGHLY EFFICIENT ELECTRONIC DESIGN AUTOMATION (EDA) TOOLS THAT WE WILL USE.

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• $125,000 - Friday the 10th of July 2015
  National Aeronautics And Space Administration
  NASA SHARED SERVICES CENTER
  WE WILL DEVELOP A PROTOTYPE OF A GPU-BASED PARALLEL BINARY DECISION DIAGRAM (BDD) SOFTWARE PACKAGE. BDDS ARE A DATA STRUCTURE THAT SATISFIES SOME SIMPLE RESTRICTIONS, RESULTING IN A UNIQUE REPRESENTATION OF A BOOLEAN FUNCTION REGARDLESS OF ITS ACTUAL IMPLEMENTATION. THIS PROPERTY OF BDDS ALLOWS THE EFFICIENT SOLUTION OF MANY PROBLEMS. THE PROPOSED TOOL WILL EXPLOIT MULTI-CORE CPUS AND THE THOUSANDS OF STREAM CORES IN THE LATEST GRAPHICS PROCESSORS (GPUS) , WHICH WERE MADE ACCESSIBLE TO PROGRAMMERS THROUGH SPECIALIZED SOFTWARE DEVELOPMENT KITS. THESE LARGE NUMBERS OF STREAM CORES IN GPUS, AND THE POSSIBILITY TO EXECUTE NON-GRAPHICS COMPUTATIONS ON THEM, OPEN UNPRECEDENTED LEVELS OF PARALLELISM AT A VERY LOW COST. IN THE LAST 8 YEARS, GPUS HAD AN INCREASING PERFORMANCE ADVANTAGE OF AN ORDER OF MAGNITUDE RELATIVE TO X86 CPUS. FURTHERMORE, THIS PERFORMANCE ADVANTAGE WILL CONTINUE TO INCREASE IN THE NEXT 20 YEARS BECAUSE OF THE SCALABILITY OF THE CHIP MANUFACTURING PROCESSES. THE TECHNICAL OBJECTIVES WILL BE TO EFFICIENTLY EXPLOIT THE GPU PARALLELISM IN ORDER TO ACCELERATE THE EXECUTION OF A BDD PACKAGE, AND TO EXPLORE HYBRID APPROACHES THAT WILL COMBINE THIS GPU-BASED BDD PACKAGE WITH OUR GPU-BASED PARALLEL SAT SOLVER THAT WE ARE CURRENTLY DEVELOPING IN A NASA SBIR PHASE II PROJECT. THE GOAL WILL BE TO ACHIEVE INCREASED SPEED, AS WELL AS SCALABILITY FOR MUCH LARGER STATE SPACES WHEN FORMALLY VERIFYING COMPLEX SOFTWARE FOR SPACE APPLICATIONS. WE ANTICIPATE INCREASE IN BOTH SPEED AND SCALABILITY BY 1 2 ORDERS OF MAGNITUDE BY THE END OF PHASE I, AND 3 4 ORDERS OF MAGNITUDE BY THE END OF PHASE II, COMPARED TO THE CURRENT APPROACHES.

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