The Collier Report of U.S. Government Contracting

Sampling of Federal Government Funding Actions/Set Asides

In order by amount of set aside monies.

• $75,000 - Monday the 14th of April 2014
  National Aeronautics And Space Administration
  NASA SHARED SERVICES CENTER
  MICROWAVE INTERFEROMETERS FOR NASA MISSIONS SUCH AS PATH EMPLOY THE GEOSTAR INSTRUMENT, CONSISTING OF 600 RECEIVERS. EACH RECEIVER REQUIRES I AND Q ADCS (ANALOG-TO-DIGITAL CONVERTERS) FOR SIGNAL DIGITIZING AT 1GHZ BEFORE FURTHER PROCESSING IN THE CROSS-CORRELATORS. POWER CONSUMPTION AS WELL AS INSTRUMENT VOLUME AND WEIGHT ARE CRITICAL IN SPACE BORN INSTRUMENTS. DURING PHASE I, PACIFIC MICROCHIP CORP. DESIGNED THE BLOCK DIAGRAMS AND CIRCUITS OF A MONOLITHIC ARRAY CONSISTING OF SIXTEEN 2-BIT ADCS. A SERIALIZER IS INTEGRATED TO REDUCE THE NUMBER OF OUTPUTS FROM 32 TO 1. THIS REDUCES THE POWER CONSUMPTION PER ADC AND RESOLVES THE PROBLEM OF WIRING CONGESTION IN THE INTERFACE WITH CROSS-CORRELATORS. FOR FURTHER POWER REDUCTION, A NOVEL METASTABILITY PROGRAMMING FEATURE IS INTEGRATED INTO THE ADC LATCHES. THE CLOCK DISTRIBUTION IS FUNDAMENTALLY SIMPLIFIED AS WELL. THE 2-WIRE SERIAL I2C (INTER-INTEGRATED CIRCUIT) INTERFACE ALLOWS ALL 1200 ADCS OF THE GEOSTAR INSTRUMENT TO BE CALIBRATED AND OPTIMIZED. PHASE I WORK PROVIDED A COMPLETE DEFINITION AND IN SILICO VALIDATION OF THE MONOLITHIC ADC ARRAY WITH SERIAL OUTPUT. PHASE II OF THE PROJECT WILL PRODUCE A FIELDABLE PRODUCT. IN ORDER TO FACILITATE THE COMMERCIALIZATION EFFORTS IN PHASE III, A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) SILICON-ON-ISOLATOR (SOI) TECHNOLOGY WILL BE USED FOR FABRICATION.

  ---

• $200,000 - Monday the 14th of April 2014
  National Aeronautics And Space Administration
  NASA SHARED SERVICES CENTER
  MICROWAVE INTERFEROMETERS FOR NASA MISSIONS SUCH AS PATH EMPLOY THE GEOSTAR INSTRUMENT, CONSISTING OF 600 RECEIVERS. EACH RECEIVER REQUIRES I AND Q ADCS (ANALOG-TO-DIGITAL CONVERTERS) FOR SIGNAL DIGITIZING AT 1GHZ BEFORE FURTHER PROCESSING IN THE CROSS-CORRELATORS. POWER CONSUMPTION AS WELL AS INSTRUMENT VOLUME AND WEIGHT ARE CRITICAL IN SPACE BORN INSTRUMENTS. DURING PHASE I, PACIFIC MICROCHIP CORP. DESIGNED THE BLOCK DIAGRAMS AND CIRCUITS OF A MONOLITHIC ARRAY CONSISTING OF SIXTEEN 2-BIT ADCS. A SERIALIZER IS INTEGRATED TO REDUCE THE NUMBER OF OUTPUTS FROM 32 TO 1. THIS REDUCES THE POWER CONSUMPTION PER ADC AND RESOLVES THE PROBLEM OF WIRING CONGESTION IN THE INTERFACE WITH CROSS-CORRELATORS. FOR FURTHER POWER REDUCTION, A NOVEL METASTABILITY PROGRAMMING FEATURE IS INTEGRATED INTO THE ADC LATCHES. THE CLOCK DISTRIBUTION IS FUNDAMENTALLY SIMPLIFIED AS WELL. THE 2-WIRE SERIAL I2C (INTER-INTEGRATED CIRCUIT) INTERFACE ALLOWS ALL 1200 ADCS OF THE GEOSTAR INSTRUMENT TO BE CALIBRATED AND OPTIMIZED. PHASE I WORK PROVIDED A COMPLETE DEFINITION AND IN SILICO VALIDATION OF THE MONOLITHIC ADC ARRAY WITH SERIAL OUTPUT. PHASE II OF THE PROJECT WILL PRODUCE A FIELDABLE PRODUCT. IN ORDER TO FACILITATE THE COMMERCIALIZATION EFFORTS IN PHASE III, A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) SILICON-ON-ISOLATOR (SOI) TECHNOLOGY WILL BE USED FOR FABRICATION.

  ---

• $124,971 - Tuesday the 8th of January 2013
  National Aeronautics And Space Administration
  NASA SHARED SERVICES CENTER
  NASA'S LATEST EFFORT IN DEVELOPING A COMMON PLATFORM FOR SPACE COMMUNICATION AND NAVIGATION SYSTEMS IS THE SPACE TELECOMMUNICATIONS RADIO SYSTEM (STRS) STANDARD. IT DEFINES ARCHITECTURE ENABLING INTEROPERABILITY OF SOFTWARE DEFINED RADIO (SDR) COMPONENTS. FUTURE PROOF, POWER CONSCIOUS ARCHITECTURES OF STRS COMPLIANT RE-CONFIGURABLE SDR TRANSCEIVERS ARE NEEDED FOR IMPLEMENTATION OF ENVISIONED SPACE COMMUNICATION SYSTEMS. PACIFIC MICROCHIP CORP. PROPOSES TO DEVELOP A HIGHLY INTEGRATED, LOW-POWER, MULTIFUNCTIONAL 56GS/S DIRECT DIGITAL MODULATION/DEMODULATION (DDM) SDR TRANSCEIVER USING 45NM SOI CMOS TECHNOLOGY. THE RESULTING STRS COMPLIANT INTEGRATED SOLUTION WILL BE RADIATION TOLERANT BY TECHNOLOGY AND DESIGN. THE DIRECT CONVERSION BASED TRANSCEIVER UTILIZES NOVEL 56GS/S D/A AND A/D CONVERTERS AND FEATURES ARBITRARY WAVEFORM GENERATION (AWG) MODE. THE AVAILABILITY OF AWG AND DDM MODES REMOVES LIMITATIONS ON THE SYNTHESIZED WAVEFORM SHAPES UP TO 28GHZ. PACIFIC MICROCHIP CORP. PROPOSES ALL-DIGITAL IMPLEMENTATION OF FREQUENCY UP- AND DOWN-CONVERSION, I/Q MODULATION AND DEMODULATION. SINCE DIGITAL POWER IS MOSTLY DYNAMIC, DIGITAL PROCESSING WILL ENABLE POWER CONSUMPTION SCALING LINEARLY WITH THE OPERATING FREQUENCY. PHASE I WORK WILL PROVIDE A COMPLETE DEFINITION AND IN-SILICO VALIDATION OF THE PROPOSED DEVICE. THE PHASE II PROGRAM WILL PRODUCE A FIELDABLE PRODUCT. IN ORDER TO FACILITATE THE COMMERCIALIZATION EFFORTS IN PHASE III, A COMMERCIAL RADIATION-TOLERANT CMOS SOI TECHNOLOGY WILL BE USED.

  ---

• $124,971 - Wednesday the 12th of December 2012
  National Aeronautics And Space Administration
  NASA SHARED SERVICES CENTER
  PACIFIC MICROCHIP CORP. OFFERS TO DESIGN AN ASIC THAT INCLUDES A CROSS-CORRELATION UNIT TOGETHER WITH THE INTERFACES TO BE CONNECTED TO THE OUTPUT OF THE GEOSTAR'S RECEIVERS, MULTIPLEXER AND OUTPUT INTERFACE FOR THE GEOSTAR'S SYSTEM-LEVEL INTEGRATION. THE PROPOSED NOVEL ASIC REQUIRED BY NASA'S PATH MISSION WILL HAVE A GREATLY REDUCED POWER CONSUMPTION COMPARED TO A FPGA BASED OR A CLASSIC ASIC BASED IMPLEMENTATIONS, INCREASED RADIATION HARDNESS AND EXTENDED OPERATING TEMPERATURE RANGE. THE PROPOSED CROSS-CORRELATION UNIT CONSISTS OF CROSS-CORRELATION CELLS WHICH ARE BASED ON NOVEL ARCHITECTURE. THE LOGIC PRIMITIVES ARE ARRANGED TO "WORK WHEN MUST" RATHER THAN TO "WORK WHEN NEED" IN THESE NOVEL CROSS-CORRELATION CELLS. THE HIGH SPEED INTERFACES THE PROPOSED ASIC WILL INCORPORATE CAN MINIMIZE THE POWER CONSUMPTION AND INCREASE THE RELIABILITY. TERMINATION RESISTORS, AMPLIFIERS, ANALOG-TO-DIGITAL-CONVERTERS REALIZED INSIDE THE ASIC WILL SAVE POWER DUE TO SHORTER INTERCONNECTS COMPARED TO INTERCONNECTS THAT ARE USED IN FPGAS. MOREOVER, THE HIGH-SPEED RECEIVERS-DESERIALIZERS COULD FURTHER SAVE THE POWER DUE TO REDUCED NUMBER OF TERMINATION RESISTORS COMPARED TO THE HIGH-SPEED INTERFACE WITH ANALOG-TO-DIGITAL CONVERTERS. THE DEEP SUBMICRON SOI CMOS TECHNOLOGY SELECTED FOR THE ASIC'S FABRICATION WILL INCREASE ITS TOLERANCE TO TOTAL IONIZING DOSE (TID) AND REDUCE THE PROBABILITY OF RADIATION INDUCED LATCH-UP. THE ASIC WILL BE DESIGNED FOLLOWING THE DESIGN FOR TESTABILITY (DFT) METHODS THAT WILL SIMPLIFY CHARACTERIZATION AND TESTING OF THE FABRICATED ASIC THUS WILL REDUCE THE RISK AND LOWER THE COST OF THE PRODUCT. PHASE I OF THE PROJECT WILL PROVIDE A COMPLETE DEFINITION OF THE PROPOSED ASIC, ITS DESIGN AND IN SILICO VALIDATION OF CRITICAL CIRCUITS. PHASE II WILL PRODUCE A FIELDABLE PRODUCT READY FOR COMMERCIALIZATION IN PHASE III.

  ---